Electronic circuits often require a voltage reference that is stable and substantially constant over temperature and power supply variations. A bandgap reference circuit is typically used to generate such a temperature-independent and power-supply-independent reference voltage. A bandgap reference circuit typically generates a bandgap voltage of approximately 1.24 volts using two transistors operating at different current densities by developing a first voltage across the first transistor having a positive temperature coefficient and second voltage across the second transistor having a negative temperature coefficient, and then combining the two voltages to generate the temperature-independent bandgap voltage.
As with many integrated circuits (ICs), bandgap reference circuits require precise resistance values in order to generate the desired bandgap voltage. However, due to process variations inherent during the fabrication of all ICs, the actual resistance values on bandgap reference circuits can vary by as much as 15-20% from their intended value, resulting in undesirable temperature related variances in the bandgap voltage.
Trimming is a technique used to improve the accuracy and yield of bandgap reference circuits and other precision ICs. Trimming typically involves the selective addition or removal of resistive “trim” elements (e.g., resistors or other resistive elements) from the bandgap reference circuit in order to “tune” the circuit's operating characteristics. Specifically, after a bandgap reference circuit has been fabricated, trimming is sometimes carried out to modify the resistance values of the resistive elements that control the differential transistors, thereby bringing the bandgap voltage to within specification.
FIG. 6 is a simplified circuit diagram showing an exemplary bandgap reference circuit 10. Bandgap reference circuit 10 generally includes first and second differential transistors Q1 and Q2 that are respectively connected in series with current sources 11-1 and 11-2 between a voltage supply (VSUPPLY) and a ground (VGROUND). A node A between transistor Q1 and current source 11-1 is connected to the inverting (−) input terminal of an operational amplifier 12, and a node B between transistor Q2 and current source 11-2 is connected to the non-inverting (+) input terminal of amplifier 12. A bandgap voltage VBANDGAP is generated at the output terminal of amplifier 12, and is fed back to a third node C1, which is connected to the base of transistor Q2 and to the first terminal of a trimmable resistor TR1. Trimmable resistor TR1 is connected between node C1 and a node C2, which is connected to the base of transistor Q1, and is also connected to ground by way of a second trimmable resistor TR2 and a bandgap diode BGD.
FIGS. 7(A) and 7(B) are diagrams showing an exemplary conventional trimmable resistor TR (i.e., either trimmable resistors TR1 or TR2 of FIG. 6). Trimmable resistor TR includes resistors RTRIM1 and RTRIM2 that are respectively connected in parallel with zener diodes (or other one-time programmable trim elements) DTRIM1 and DTRIM2. External contact pads P1 to P3 are connected to trimmable resistor TR such that zener diode DTRIM1 is connected between pads P1 and P2, and zener diode DTRIM2 is connected between pads P2 and P3. In a first programmed state (e.g., as shown in FIG. 7(A)), both zener diodes DTRIM1 and DTRIM2 function normally to resist current flow in the direction of current path IC, thereby forcing current path IC to flow through resistors RTRIM1 and RTRIM2. To reduce the resistance of trimmable resistor TR, one or both of zener diodes DTRIM1 and DTRIM2 are destroyed (sometimes referred to as “blown” or “zapped”), thereby creating a short circuit that bypasses the associated resistor RTRIM1 or RTRIM2. For example, as indicated in FIG. 7(B), a high voltage potential applied across pads P1 and P2 “blows” (short circuits) zener diode DTRIM1, allowing current path IC to bypass resistor RTRIM1, thereby effectively reducing the resistance of trimmable resistor TR by approximately the resistance of resistor RTRIM1. Similarly, a high voltage potential applied across pads P2 and P3 would “blow” zener diode DTRIM2, thereby effectively reducing the resistance of trimmable resistor TR by the resistance of resistor RTRIM2.
FIG. 8(A) and 8(B) are side elevation and top plan views showing a conventional test/trim apparatus 20 positioned over a wafer 30 that includes multiple die 35 fabricated according to known techniques, where each die 35 includes one or more bandgap reference circuits 10 (indicated in FIG. 8(B)). Test/trim apparatus 20 is movable relative to wafer 30, and includes several probes 25 that are brought into contact with test/trim contact pads formed on a selected die (e.g., trim pads P1 to P3; see FIG. 7(A)). Specifically, during the conventional trimming procedure, test/trim apparatus 20 is positioned over a selected die, and then moved toward the selected die (as indicated by the arrows in FIG. 8(A)) such that probes 25 comes into contact with the test/trim contact pads formed on or adjacent to the selected die. Power is then transmitted to the selected die through selected probes 25, causing, for example, the bandgap reference circuit to generate bandgap voltage VBANDGAP in the manner described above. One of the probes passes the generated bandgap voltage VBANDGAP to a control circuit (not shown) that is operably coupled to test/trim apparatus 20, and the generated bandgap voltage VBANDGAP is compared with a stored value (sometimes referred to as a “magic number”). When the generated bandgap voltage VBANDGAP differs from the stored value, one or more of the trimmable resistors is trimmed in the manner described above to modify the effective resistance, thereby bringing the generated bandgap voltage VBANDGAP into compliance with the stored value. Test/trim apparatus 20 is then moved to a next die 35, and the process is repeated until all of the die 35 on wafer 30 are tested and trimmed.
As indicated in FIG. 9, a problem associated with the conventional test/trim procedure described above is that stray (parasitic) capacitances CS associated with test probes 25 of test/trim apparatus 20 significantly increases the response time of bandgap reference circuit 10, thereby significantly increasing the time required to perform the test/trim procedure. Due to the operating characteristics of bandgap reference circuit 10 (i.e., relatively high resistance values and relatively low currents), even a small additional capacitance applied to nodes C1 and C2 (i.e., to the terminals of trimmable resistors TR1 and TR2) can add a significant capacitance to bandgap reference circuit 10. Therefore, when probes 25 are connected to trim pads P1 to P3 (as depicted in a simplified manner in Fig. ZZ), stray capacitance CS becomes coupled to the bases of transistors Q1 and Q2, which control amplifier 12 to generate bandgap voltage VBANDGAP, thereby causing a significant delay in the time required for bandgap reference circuit 10 to reach a stable operating condition suitable for performing the test/trim procedure. By increasing the time required to perform the test/trim procedure, overall manufacturing costs are increased, thereby reducing profits.
What is needed is method for reducing the amount of time required to perform a test/trim procedure by minimizing the delay introduced by stray capacitance applied by the test/trim apparatus probes to bandgap reference circuits. What is also needed is a bandgap reference circuit having trim elements that are arranged to facilitate the reduced-time test/trim procedure.